Principal Digital Engineer (DFT Design)
Core
Design complex automotive Power Management ICs (PMIC) focusing on digital Design for Test (DFT) and test pattern validation to meet ASIL-B/D requirements.
Role type
Principal Digital DFT Engineer
Builds
Automotive PMIC chips with integrated digital control circuitry
Domain
Automotive semiconductor / Digital IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
DFT/Scan insertion, ATPG, LogicBIST insertion, RTL coding (Verilog/System Verilog), gate-level simulation, timing constraints, synthesis, P&R interaction, CDC analysis, test pattern validation, ATE debugging
Preferred skills
Mixed-signal design experience, automotive ASIL test requirements knowledge, Tetramax tool experience
Technologies
Synopsys, Cadence, Mentor, Siemens, Tetramax
Responsibilities
Insert DFT/Scan on digital logic and improve scan coverage; deliver and validate test patterns on silicon; insert LogicBIST during synthesis/RTL; reduce ATE tester time; participate in digital design flow from micro-architecture to timing analysis; debug scan pattern fails; write DFT specifications and design documents; organize design reviews.
Seniority
Principal, hands-on IC design with strategy influence