Principal Engineer-Physical Design
Core
Lead end-to-end physical design execution of large-scale, high-performance SoCs (3nm/5nm) from floorplanning through tape-out, optimizing PPA targets.
Role type
Senior Principal Engineer / Senior Manager – Physical Design Lead
Builds
Next-generation SoC products for Automotive, Industrial, Infrastructure, and IoT markets
Domain
Semiconductor / ASIC Physical Design / Advanced Node (3nm/5nm)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Floorplanning, Power Planning, Placement, Clock Tree Synthesis, Routing, Timing Closure, Signal Integrity, IR/EM Closure, Physical Verification, Low-Power Architecture, Cross-functional Team Leadership, Tape-out Management
Preferred skills
High-speed SerDes integration, Mixed-signal/analog IP integration, Network-on-Chip (NoC), Chiplet/Multi-die architectures, Advanced packaging, AI/HPC/Networking product experience
Technologies
UPF/CPF, DVFS, Power Gating, Clock Gating, Multi-voltage domains, GDS signoff flows
Responsibilities
Lead end-to-end physical design execution from floorplanning to GDS signoff; Own implementation strategy, risk management, and tape-out readiness; Drive timing closure for complex multi-clock, high-frequency designs; Mentor senior physical design engineers and establish implementation excellence
Seniority
Senior Principal / Senior Manager, hands-on IC with strategic leadership