Principal Engineer- Design Verification
Core
Lead verification strategy and execution for next-generation UA Link Switch products, ensuring first-silicon success for high-performance interconnect and switching solutions.
Role type
Principal Verification Lead (SoC/ASIC)
Builds
Scalable UVM/System Verilog verification environments for complex SoC and subsystem designs
Domain
Semiconductor, Memory Interface, High-speed Digital Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
System Verilog, UVM, Assertion-Based Verification (SVA), Functional Coverage, Code Coverage, Regression Infrastructure, Verification Closure, Debug & Root-Cause Analysis, Cross-functional Team Leadership
Preferred skills
Formal Verification, Emulation, FPGA Prototyping, Performance Verification, Mixed Hardware/Firmware Verification, Geographically Distributed Team Management
Technologies
UVM, System Verilog, SVA, SerDes, PCIe, CXL, Ethernet, UALink, UCIe
Responsibilities
Define verification strategy and execution plan; Lead verification architecture and testbench development; Drive scalable verification environments; Collaborate with architecture, design, firmware, and silicon bring-up teams; Develop verification plans for functionality, performance, and reliability; Lead debug and root-cause analysis; Mentor verification engineers and establish best practices
Seniority
Principal, hands-on IC with strategic leadership
