Sr Staff Package Design Engineer
Core
Design and develop package and interconnect methods for power SiP/modules, WLCSP, and multi-chip modules, focusing on substrate, die interconnection, and production ramp-up.
Role type
Sr Staff Package Design Engineer
Builds
Power SiP/modules, WLCSP, multi-chip modules with substrate or embedded die/capacitor
Domain
Semiconductor packaging (Power SiP, Wafer Level Packaging, Flip Chip)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Package development, assembly process knowledge, qualification methods, SPC, statistical analysis, Cu FSM/BGBM technologies, DOE optimization, process integration, production controls, package design rules
Preferred skills
Cu FSM/BGBM technologies, advanced packaging innovations
Technologies
Cu RDL, Taiko BG, Glass carrier, LGA, PCB
Responsibilities
Design and develop package and interconnect methods; Develop Cu RDL with seed layer and backside metal deposit; Perform wafer thinning development; Define substrate and die interconnection requirements; Qualify packages for consumer, industrial, and automotive applications; Benchmark and select materials, processes, and OSAT/CM partners; Work with OSAT/CM to optimize processes and establish specs; Resolve process integration issues; Establish production controls and monitor quality; Ensure smooth transition into production; Address customer complaints; Develop and maintain technical expertise on packaging innovations; Participate in packaging roadmap development; Establish and maintain package design rules
Seniority
Sr Staff, hands-on IC
