HPC SoC Timing Design Engineer/Leader
Core
Designing and optimizing timing for large-scale, complex High-Performance SoCs used in automotive applications (CASE: Connected, Autonomous, Sharing, Electrification) to ensure efficient development and performance.
Role type
Senior IC HPC SoC Timing Design Engineer/Leader
Builds
High-performance automotive SoCs for connected, autonomous, and electrified vehicles
Domain
Automotive electronics / Semiconductor Design / Digital Backend
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Static Timing Analysis (STA), Timing Constraint Analysis, Logic Synthesis, Digital LSI design, 3nm process node experience, Cross-functional collaboration with global teams (Vietnam/India)
Preferred skills
Hardware description languages (Verilog-HDL), Management experience, Business-level English or Japanese
Technologies
STA tools, SDC tools, Synthesis tools, 3nm process nodes
Responsibilities
Perform static timing analysis using commercial tools; Validate timing constraints using commercial and in-house tools; Execute logic synthesis using commercial tools; Collaborate with overseas design centers on timing design tasks.
Seniority
Senior, hands-on IC with leadership potential
