Staff Engineer, Physical Design
Core
Lead subsystem- and block-level physical implementation and closure for complex hierarchical SoCs at advanced technology nodes, ensuring alignment with overarching SoC strategies.
Role type
Staff Physical Design Engineer (Subsystem/Block Level)
Builds
Subsystem and block-level physical implementations for complex hierarchical SoCs
Domain
Semiconductor / SoC Physical Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Timing closure and constraint management, Congestion analysis and resolution, Power integrity and power-aware implementation, Block and subsystem-level physical design flows, Clock domain partitioning, Clock tree architecture, Skew management, Clock gating, Scripting and automation (Tcl, Python, Perl), Low-power design techniques
Preferred skills
SoC-level floorplanning understanding, Cross-functional collaboration with RTL/STA/Power/Verification teams, Mentorship of physical design engineers
Technologies
Synopsys ICC2, Fusion Compiler, PrimeTime, Cadence Innovus, Tempus, Certus
Responsibilities
Lead block- and subsystem-level physical design closure, Collaborate with SoC-level teams on clocking strategies and floorplanning intent, Develop and scale subsystem closure methodologies, Mentor physical design engineers, Work cross-functionally with RTL, STA, power, and verification teams, Mitigate physical design risks
Seniority
Staff, hands-on IC with mentorship
