Sr Mask Design Engineer
Core
Layout high performance Analog and Mixed Signal circuits using Cadence Design Suite, performing IP level tasks including device placement, routing, matching, shielding, and parasitic-aware practices.
Role type
Senior IC Mask Design Engineer (Analog/Mixed Signal)
Builds
Reusable IP blocks and top-level macro layouts for embedded semiconductor solutions
Domain
Semiconductor IC Design (Analog, Mixed Signal, Power)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog IC layout, Mixed Signal layout, Device placement, Routing (IC617 Virtuoso), Design rule verification (Assura, Calibre, PVS), QRC extraction, IR drop analysis, p2p resistance analysis, Schematic-driven layout
Preferred skills
BCD technology experience, VSR/VCAR auto routing, Constraints-driven layout methodology
Technologies
Cadence Design Suite, Assura, Calibre, PVS, IC617 Virtuoso, Modgens, Clones
Responsibilities
Liaise with analog designers on circuit requirements (power, matching, sensitivity, latch-up, ESD), Work with CAD/CAE engineers to improve processes, Create robust layout methodologies for IP re-use
Seniority
Senior, hands-on IC
