IP验证工程师-Data（上海）
Core
Build and maintain UVM verification environments for chip interconnect protocols, ensuring high-quality delivery through automation and coverage analysis.
Role type
Senior IC verification engineer (chip interconnect)
Builds
Production chip designs supporting high-speed interconnects
Domain
Semiconductor / Chip Design / Interconnect Protocols
Required skills
UVM, System Verilog, Perl, Python, C/C++, Makefile, RTL/FW co-simulation, GLS simulation, performance validation, power-aware simulation, regression analysis
Preferred skills
CXL, CCIX, NVMe, SR-IOV, S-IOV compression algorithms
Technologies
UVM, System Verilog, Makefile, Perl, Python, C/C++, AMBA ACE-lite 4/5, SMMU, IO Coherency, Scheduler
Responsibilities
Build UVM verification environments; Develop automated and reusable verification environments; Define verification plans and collect coverage; Execute performance and power-aware simulations; Assist design teams in debugging and analyze regression results; Improve and refine verification processes.
