Formal Design Verification Engineer
Core
Lead formal verification of components used in Fabric Interconnect, developing environments and strategies to ensure design quality.
Role type
Senior IC formal verification engineer (fabric interconnects)
Builds
Pre-silicon subsystems and IP for fabric interconnects
Domain
Semiconductor hardware verification, interconnect protocols
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
formal verification, UVM, System Verilog Test Bench (SVTB), Python scripting, generative AI application, protocol verification (CHI, AMBA), IP verification lifecycle management, technical leadership
Preferred skills
experience with fabric interconnects, coherency, virtualization, security, interrupts, PCIe, CXL, protocol bridges
Technologies
UVM, System Verilog, Python, CHI, AMBA
Responsibilities
Own or lead verification of components used in Fabric Interconnect; Develop Formal-based verification environments and run/debug simulations; Innovate to improve verification efficiency through methodologies or tools; Coach and mentor others in areas of expertise
Seniority
Senior, hands-on IC with technical leadership
