Senior RTL Engineer, Interconnect Design
Core
Designing and delivering critical on- and off-chip interconnect components (NoC, switches, routers, protocol bridges) for custom AI accelerator platforms to power frontier models.
Role type
Senior hands-on IC RTL Engineer (Interconnect/SoC)
Builds
Custom AI-native silicon and tightly integrated systems for OpenAI's supercomputing platform
Domain
AI Hardware / SoC Design / Interconnect
Deliverable
production ML models
Required skills
Microarchitecture definition, RTL implementation (Verilog/SystemVerilog), NoC design, Protocol design (AXI, PCIe, CXL), Performance analysis, Verification strategy, Physical design convergence, Technical leadership
Preferred skills
AI accelerator/GPU/CPUs interconnect experience, Memory consistency/RAS, NoC performance modeling, FPGA prototyping, First-generation silicon program leadership
Technologies
Verilog, SystemVerilog, AXI, APB, CXL, PCIe, Ethernet, NoC, FPGA
Responsibilities
Own microarchitecture and RTL design of major SoC interconnect components; Drive third-party engagements for novel protocols; Perform direct RTL coding; Collaborate on solution execution plans; Analyze traffic patterns and optimize interconnect behavior; Develop verification strategies and coverage plans; Partner with physical design teams for timing/power/area closure; Provide technical leadership and mentorship
Seniority
Senior, hands-on IC with mentorship responsibilities
