Senior DFT Engineer
Core
Design and implement Digital Design for Test (DFT) solutions for wireless System-on-Chips (SoCs) to ensure testability, debuggability, and yield for IoT devices.
Role type
Senior DFT Engineer
Builds
Wireless SoCs (Wi-Fi HaLow/IoT chips)
Domain
Semiconductor / Wireless Connectivity / Digital IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Scan insertion/stitching, ATPG setup, JTAG, simulation, debug, scan DRC analysis, hierarchical DFT methodologies, RTL coding, verification, silicon bring-up, MBIST integration, IEEE 1500 wrappers, ATE bring-up
Preferred skills
Post-silicon debug, yield analysis, DFT scripting/automation, cross-functional collaboration
Technologies
IEEE 1149.1, IEEE 1500, BSDL, SDF, WGL, STIL, OPCG, JTAG, ATE
Responsibilities
Define DFT architecture and coverage goals; Architect and implement SCAN solutions; Develop at-speed test methodologies; Implement low-power DFT techniques; Integrate MBIST and diagnostics; Generate and validate ATPG and MBIST patterns; Drive silicon debug and yield analysis.
Seniority
Senior, hands-on IC
