Senior Verification Design Automation Engineer
Core
Building and scaling automation infrastructure for advanced ASIC verification environments, including AI-based flows and execution environments.
Role type
Senior IC verification design automation engineer
Builds
Scalable regression flows, dashboards, reporting utilities, and triage automation for block, subsystem, and SoC-level verification
Domain
Semiconductor / ASIC verification / High-performance computing / AI networking
Deliverable
production ML models | infrastructure
Required skills
Python, Perl, Tcl, shell scripting, Linux environments, EDA tool integrations, simulation/coverage/lint/formal/emulation workflows, distributed compute infrastructure management, debugging complex verification environments
Preferred skills
SystemVerilog, UVM, GitHub Actions, job schedulers, data analytics, regression management, coverage tracking
Technologies
Python, Perl, Tcl, shell scripting, Make, Linux, GitHub Actions, EDA tools
Responsibilities
Develop and maintain AI-based verification flows and automation frameworks; Build scalable regression flows and reporting utilities; Create automation scripts and workflow integrations; Support simulation, coverage, lint, formal, emulation, and CI flows; Manage and troubleshoot compute, storage, licensing, and job-dispatch infrastructure; Drive automation improvements for reliability and scalability across distributed teams
Seniority
Senior, hands-on IC
