Senior RTL Design Engineer
Core
Design component units of the Reconfigurable Dataflow Unit (RDU) ASICs for SambaNova's full-stack generative AI platform, covering RTL implementation, PPA trade-offs, and silicon bring-up.
Role type
Senior IC RTL Design Engineer (ASIC)
Builds
Compute datapath, on-chip network, and memory subsystems for AI accelerators
Domain
Semiconductor / AI Hardware Acceleration
Deliverable
production ML models
Required skills
SystemVerilog RTL design, computer architecture, digital logic design, PPA trade-off analysis, industry-standard interconnects (AXI, PCIe, Ethernet, HBM/DDR), digital logic synthesis, static timing analysis, linting, clock domain crossing, logical equivalence checking, SystemVerilog Assertions, hardware performance analysis, Git, Python scripting, Linux shell
Preferred skills
Full ASIC development cycle experience, AI workload acceleration techniques, low-power design (clock gating, DVFS), emulation or FPGA prototyping
Technologies
SystemVerilog, Python, Linux, AXI, PCIe, Ethernet, HBM, DDR, Git
Responsibilities
Write and debug RTL for assigned blocks, contribute to microarchitecture specifications, carry blocks through implementation and tape-out, collaborate with verification and physical design teams, perform timing closure and quality gate checks
Seniority
Senior, hands-on IC
