Design Verification Engineer
Core
Build verification environments and plans for complex chip-level control, initialization, sequencing, and state transitions on the RDU AI chip.
Role type
Senior IC design verification engineer (DFT)
Builds
RDU chips for machine learning and AI workloads
Domain
Semiconductor hardware design, AI/ML infrastructure
Deliverable
production ML models
Required skills
SystemVerilog, UVM, constrained-random verification, functional coverage, assertion-based verification, simulation debug, scripting (Python/Perl/TCL), SoC architecture, digital design
Preferred skills
CDC/RDC concepts, AI tool fluency for verification
Technologies
SystemVerilog, UVM, Python, Perl, TCL, shell scripting
Responsibilities
Develop and execute comprehensive verification plans for complex chip-level control and initialization features; Develop SystemVerilog/UVM based verification environments, test sequences, checkers, assertions, and functional coverage; Verify complex sequencing, dependencies, state transitions, and recovery scenarios across multiple chip subsystems; Develop directed and constrained-random tests to identify architectural and implementation corner cases; Debug simulation and regression failures and work with design teams to root-cause and resolve issues; Analyze regression failures, functional and code coverage and drive verification to closure
Seniority
Senior, hands-on IC
