Staff Layout Engineer
Core
Designing and verifying IC layouts for memory, I/O, and standard cells in advanced submicron processes.
Role type
Staff IC Layout Engineer
Builds
Physical layouts for memory, I/O, and standard cell libraries
Domain
Semiconductor / IC Design
Required skills
IC layout design, Cadence Virtuoso, CALIBRE verification, DRC/LVS/ERC/Antenna/Electro Migration checks, floor-planning, hierarchy layout, chip integration, memory topology knowledge, SKILL programming, project management
Preferred skills
Analog layout, memory compiler experience, script programming, team leadership, new technology review leadership
Technologies
Cadence Virtuoso, CALIBRE, Hercules
Responsibilities
Apply layout guidelines and process rules for quality designs, schedule and floor-plan layouts, complete layouts and verification independently, lead or train junior engineers, compile documentation for layout methodology and flow
Seniority
Staff, hands-on IC with team leadership