Staff Engineer Analog Layout
Core
Design, optimize, and deliver high-performance semiconductor solutions for IO circuits, subsystems, and top-level layouts using advanced technology nodes.
Role type
Staff Engineer Analog Layout
Builds
IO circuit blocks, subsystems, and top-level chip layouts
Domain
Semiconductor / Analog IC Design
Required skills
IO circuit layout, floor planning, routing, layout verification, IR drop analysis, EM analysis, submicron CMOS technology, project scheduling, team leadership
Preferred skills
Methodology improvement, cross-functional collaboration, coaching junior engineers
Technologies
Cadence Virtuoso-VXL
Responsibilities
Perform IO circuit block, subsystem, and top-level layout and verification; Lead or co-lead layout design including floor planning and resolving violations; Conduct layout design reviews; Plan project schedules and distribute tasks; Guide and coach junior engineers
Seniority
Staff, hands-on IC with mentorship
