Senior Engineer Digital Verification and Methodology
Core
Senior Engineer responsible for digital verification methodology, creating verification plans, and developing reusable verification environments for integrated circuits.
Role type
Senior IC verification engineer (methodology)
Builds
Scalable verification environments and reusable verification IP for integrated circuits
Domain
Semiconductor / Digital IC Design
Required skills
SystemVerilog, UVM, constrained random verification, directed verification, coverage analysis, requirements definition, test scenario creation, verification planning, automation, digital circuit theory
Preferred skills
AI-based verification methodologies, workflow automation, user enablement
Technologies
SystemVerilog, UVM
Responsibilities
Create verification plans and translate requirements into test scenarios, checkers, assertions, and coverage goals; Develop and maintain SystemVerilog and UVM environments and reusable verification IP; Execute constrained random and directed verification and analyze regressions and coverage; Develop and maintain reusable verification methodologies and automation standards; Own methodology capabilities including requirements definition, implementation, and documentation; Evaluate and apply AI-based methodologies for verification planning and test generation; Collaborate with concept, design, and application engineering teams to drive verification scope to completion
