Senior Staff Engineer, Digital Verification and Methodology
Core
Lead functional verification for advanced integrated circuits (ASIC, SoC, FPGA) by defining strategies, architecting testbenches, and ensuring quality sign-off.
Role type
Senior Staff Engineer, Digital Verification and Methodology
Builds
Reusable SystemVerilog UVM environments, scalable testbenches, and verification methodologies for global development sites.
Domain
Semiconductor / Hardware Design / Digital Verification
Required skills
SystemVerilog, UVM, constrained-random verification, assertion-based verification, functional coverage, object-oriented testbench architecture, verification strategy, specification-to-test translation, hardware-software interaction debugging
Preferred skills
Experience with global distributed teams, automation of tool flows, metric-driven coverage closure
Technologies
SystemVerilog, UVM, OVM, Verdi, VCS, Questa, Xcelium
Responsibilities
Lead end-to-end verification strategy from requirements analysis through sign-off; Architect reusable SystemVerilog UVM environments and scalable object-oriented testbenches; Implement constrained-random and assertion-based verification with robust functional coverage; Drive metric-driven coverage closure and establish clear quality criteria; Translate specifications and microarchitecture into tests, checkers, coverage models, and sign-off evidence; Improve verification methodologies, automation, and tool flows across projects and development sites; Collaborate with design, firmware, and system teams to debug issues and ensure reliable hardware-software interaction
Seniority
Senior Staff, hands-on IC with strategic scope
