Senior Design Verification Engineer
Core
Build scalable constrained random verification environments in System Verilog and create comprehensive test plans to address functional scenarios.
Role type
Senior Design Verification Engineer
Builds
Verification environments, test suites, and coverage metrics for hardware/software systems
Domain
Semiconductor / Hardware Verification
Required skills
System Verilog, UVM, constrained random verification, coverage-driven verification, test plan creation, CI/CD automation, Agile methodologies
Preferred skills
Hardware debugging, customer issue resolution
Technologies
System Verilog, UVM, CI/CD tools
Responsibilities
Build scalable constrained random verification environments, Create comprehensive test plans, Execute test plans and track coverage metrics, Create and enhance verification environments with sequences and assertions, Automate test execution for CI/CD flow, Handle on-call responsibilities for hardware issues
Seniority
Senior, hands-on IC
