Senior Staff Engineer Digital IP (f/m/div)
Core
Design and deliver reusable digital IP blocks (micro-architecture, RTL, integration) for semiconductor products.
Role type
Senior Staff Engineer Digital IP
Builds
Reusable, configurable, integration-ready IP blocks for semiconductor products
Domain
Semiconductor / Digital IP Design
Required skills
Micro-architecture design, SystemVerilog/Verilog RTL coding, RTL release execution, Design documentation, Integration support, Debugging block/system-level issues, Communication protocols (I2C, UART, SPI, AHB/APB, Audio)
Preferred skills
Python scripting for automation, AI-assisted engineering for RTL development, Knowledge of DFT/ATPG flows
Technologies
SystemVerilog, Verilog, Python, Git, Perforce, UNIX, Windows
Responsibilities
Execute hands-on digital IP design including micro-architecture refinement and RTL implementation, Develop high-quality RTL for reusable IP blocks, Translate IP roadmap requirements into executable design plans, Drive design quality closure through lint, CDC, RDC, synthesis, and DFT checks, Debug and resolve design issues in collaboration with Verification, Architecture, and System teams, Support development of communication and peripheral IPs, Work with automated RTL development flows to improve reuse and productivity
Seniority
Senior Staff, hands-on IC
