Sr. Staff ASIC Design Engineer
Core
Design and implement high-performance AI ASICs by authoring micro-architecture specifications and integrating novel computational accelerator units with compute, interconnects, and networking.
Role type
Sr. Staff ASIC Design Engineer
Builds
High-performance AI inference ASICs
Domain
Semiconductor / AI Hardware
Deliverable
production ML models
Required skills
RTL logic design (Verilog/System Verilog), IP integration (CPU into SoC), ARM/RISC-V/MIPS architectures, AMBA/APB/AXI protocols, low power design (UPF), timing closure, multi-million gate ASIC development
Preferred skills
High-frequency timing closure, AI architecture exploration (convolution, transformer)
Technologies
Verilog, System Verilog, UPF, AMBA, AXI, SPI, eMMC, MII, GPIO, I2C
Responsibilities
Author micro-architecture specifications; Architect and implement complex RTL designs; Integrate CPU and other relevant IPs; Collaborate with physical design team for timing and power optimization; Analyze code coverage; Perform diagnostic and post-silicon validation tests
Seniority
Sr. Staff, hands-on IC
