Senior Staff Engineer Design
Core
Develop micro-architecture and RTL coding for IP development in System Verilog/Verilog, manage digital IP roadmap, and ensure robustness through comprehensive quality checks.
Role type
Senior Staff Engineer Design (Digital IP)
Builds
Digital IP blocks for power systems and IoT solutions
Domain
Semiconductor / Digital Hardware Design
Required skills
System Verilog, Verilog, AHB/APB bus protocols, RTL development, technical leadership, debugging, Python scripting, automated RTL flows, release management
Preferred skills
IO controller design, AI tools for RTL optimization, cross-functional collaboration
Technologies
System Verilog, Verilog, Python, Git, UNIX, Windows, MS Office
Responsibilities
Develop micro-architecture and RTL coding for IP, manage digital IP roadmap, perform quality checks (Lint, CDC, RDC, synthesis, DFT, ATPG), establish processes to prevent bugs, lead and mentor junior engineers
Seniority
Senior Staff, hands-on IC with leadership
