Digital IP Design Engineer (f/m/d)
Core
Develop and implement digital IP and logic designs for complex Mixed-Signal System-on-Chips (SoCs), including automotive microprocessors, application processors, and AI/ML cores.
Role type
Senior IC digital IP design engineer
Builds
Interface components, DSP subsystems, and next-generation AI/ML/RISC-V IPs for automotive and networking products
Domain
Semiconductor design, automotive, networking, AI/ML
Deliverable
production ML models | product features
Required skills
Digital IP design, Mixed-Signal SoC design, RTL design (Verilog/SystemVerilog), Lint/CDC/RDC verification, IP synthesis, timing analysis, DFT implementation, AMBA protocols (AHB/AXI/ACE/CHI), memory systems (DDR/LPDDR), CPU architecture (RISC-V/AI accelerators), Python/Perl/TCL scripting, pre-silicon/post-silicon debugging
Preferred skills
AI-based design tools, conversational German
Technologies
Verilog, SystemVerilog, Python, Perl, TCL, Shell, FPGA, simulation/emulation tools
Responsibilities
Develop high-quality, area-optimal, low-power RTL designs; collaborate with hardware/software teams to define features and interfaces; perform design verification, simulation, and debugging; conduct synthesis and timing analysis; ensure DFT compliance; generate design documentation; troubleshoot design issues throughout the lifecycle.
Seniority
Senior, hands-on IC
