Lead Design Engineer
Core
Lead the end-to-end RTL design, micro-architecture definition, and integration of complex SoC, subsystem, and IP blocks.
Role type
Senior IC digital design engineer (SoC/Subsystem/IP)
Builds
Reusable, implementation-ready digital logic blocks and subsystems for semiconductor chips
Domain
Semiconductor / Digital SoC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
RTL design (Verilog/SystemVerilog), Micro-architecture definition, Digital design fundamentals (FSM, pipelines, clock/reset), AMBA protocols (AXI, AHB, APB), Interconnect design, Debugging (simulation/synthesis/integration), Design closure, Scripting (Python/Perl/Tcl/Shell)
Preferred skills
PCIe/DDR/NoC design, Low-power methodologies (UPF/CPF), Formal verification, Silicon debug, Team leadership
Technologies
Verilog, SystemVerilog, Python, Perl, Tcl, Shell, AXI, AHB, APB
Responsibilities
Translate architecture requirements into detailed micro-architecture and implementation plans; Develop high-quality RTL for key blocks like interconnects, controllers, and memory interfaces; Drive block-level and subsystem-level design integration and resolve timing/power/area issues; Collaborate with verification and physical design teams to ensure design closure; Mentor junior engineers and drive design methodology improvements.
Seniority
Senior, hands-on IC
