Principal Engineer Design
Core
Own architectural timing intent, constraint hygiene, and complete timing sign-off for complex, multi-million gate SoCs, driving multi-mode multi-corner (MMMC) timing closure from block-level to full-chip integration.
Role type
Principal Engineer Design (Static Timing Analysis)
Builds
Complex, multi-million gate System-on-Chip (SoC) designs
Domain
Semiconductor / VLSI / Hardware Design
Required skills
Static Timing Analysis (STA), Multi-mode Multi-corner (MMMC) analysis, Engineering Change Order (ECO) generation, Signal Integrity analysis, DFT mode timing validation, Tcl scripting, Python/Perl scripting, Constraint management (SDC), Cross-functional collaboration
Preferred skills
Advanced process node experience, Clock-tree synthesis (CTS) knowledge, Routing optimization expertise
Technologies
Synopsys PrimeTime, Cadence Tempus, Tweaker, PT DMSA/Primeclosure, Tcl, Python, Perl
Responsibilities
Lead and execute block-level and full-chip timing closure; Generate ECOs to fix setup, hold, and signal integrity violations; Architect and execute robust MMMC sign-off environments; Manage hierarchical constraint promotion and validation; Analyze crosstalk-induced noise and glitch propagation; Validate constraints across Scan, At-Speed, and BIST modes; Write production-grade Tcl scripts for automation; Build regression suites using Python or Perl
Seniority
Principal, hands-on IC
