Principal Engineer DSP Design
Core
Architect and simulate DSP signal chains for automotive Ethernet PHYs, implementing DSP algorithms in Verilog/System Verilog and translating MATLAB/C++ models into synthesizable HDL.
Role type
Principal Engineer DSP Design (Hardware/Algorithm)
Builds
Automotive Ethernet PHYs with high-speed wireline DSP capabilities
Domain
Automotive semiconductors, high-speed digital communications
Deliverable
production ML models
Required skills
DSP fundamentals (probability/statistics), high-speed wireline DSP (FFE/DFE, CDR, MLSD/Viterbi, FEC), Verilog/System Verilog, C++, MATLAB, fixed-point modeling, RTL design
Technologies
Verilog, System Verilog, MATLAB, C++, Ethernet PHY
Responsibilities
Architect and simulate DSP signal chains for automotive Ethernet PHYs; Implement DSP algorithms (filtering, error correction, echo cancellation, equalization) in HDL; Collaborate with algorithm and systems teams to define hardware architecture; Translate fixed-point MATLAB/C/C++ models into synthesizable HDL; Design and implement timing recovery/synchronization blocks (CDR, tracking loops); Contribute to detection and coding/FEC integration; Support silicon bring-up and lab debug.
Seniority
Principal, hands-on IC
