DSP Engineer
Core
Implementing and optimizing DSP algorithms for Automotive Ethernet PHY architecture, specifically for 100/1000BASE‑T1 and Multi‑Gig standards.
Role type
Senior IC Digital Signal Processing Engineer (Automotive Ethernet PHY)
Builds
Automotive Ethernet PHY datapath blocks and system-level analysis models
Domain
Automotive semiconductor / High-speed communication protocols
Deliverable
production ML models | product features
Required skills
DSP fundamentals, PHY-layer DSP blocks, RTL design (Verilog/SystemVerilog), MATLAB/Simulink, Python, C/C++ modeling, synthesis, STA, CDC, linting
Preferred skills
Automotive Ethernet PHY development, DFT, post-silicon bring-up, backend timing closure, UVM environments, formal verification
Technologies
Verilog, SystemVerilog, MATLAB, Simulink, Python, C, C++
Responsibilities
Implement and optimize DSP architecture for Automotive Ethernet PHY; Develop high-quality RTL for DSP datapath blocks; Collaborate with Verification/Validation for debugging and coverage closure; Work with DFT, System Architecture, IC Integration, and Backend teams for constraints and timing closure; Develop MATLAB/Python models and support system-level analysis
Seniority
Senior, hands-on IC