Principal Engineer DSP PHY Digital Design
Core
Architect and simulate DSP signal chains for automotive Ethernet PHYs, defining features, performance targets, and algorithm specs for mixed-signal and digital teams.
Role type
Principal Engineer, Digital Design (PHY/DSP)
Builds
Automotive Ethernet PHYs (wireline communication interfaces)
Domain
Automotive semiconductor / High-speed digital communications
Deliverable
production ML models
Required skills
RTL Design and Verification, Equalization and adaptation algorithms (FFE/DFE, adaptive filtering), Timing recovery/synchronization (CDR, tracking loops), Coding/FEC integration, C++, MATLAB, Fixed-point modeling, Verification metrics (BER/FER, convergence time)
Preferred skills
Automotive Ethernet PHY/SerDes constraints, ADC-based receiver architectures, RTL-friendly spec translation, Link startup/training/autoneg concepts, IEEE 802.3 standards
Technologies
C++, MATLAB, Python, RTL, FFE, DFE, CDR, FEC, IEEE 802.3
Responsibilities
Architect and simulate DSP signal chains for automotive Ethernet PHYs; Develop equalization and adaptation algorithms for wireline channels; Design and implement timing recovery/synchronization blocks; Contribute to detection and coding/FEC integration; Build bit-true/fixed-point models and reference implementations; Define verification metrics and stress tests; Support silicon bring-up and lab debug.
Seniority
Principal, hands-on IC with strategy & mentorship
