Analog & Mixed-Signal IC Design Lead Engineer
Core
Lead the definition, execution, and delivery of next-generation high-speed interconnect silicon, including SerDes front-ends, serial links, and precision data converters.
Role type
Senior IC design lead (analog/mixed-signal, high-speed wireline)
Builds
High-speed interconnect silicon, SerDes front-ends, optical interconnect ICs, and multi-Gbps signal chains
Domain
Semiconductor, high-speed analog/mixed-signal IC design
Deliverable
production ML models | product features
Required skills
High-speed wireline link design, SerDes front-end architecture, advanced CMOS/FinFET/SOI design, transistor-level schematic development, pre-silicon simulation, post-silicon bring-up, team leadership, external contractor/IP vendor management
Preferred skills
56G/112G PAM-4 SerDes, UCIe, optical module ICs (TOSA/ROSA), DSP-based link architectures, Cadence Virtuoso/Spectre, lab characterization
Technologies
PCIe, UCIe, Ethernet, FinFET (7–16 nm), SOI, Cadence Virtuoso, Spectre, APS, Ultrasim
Responsibilities
Lead analog/mixed-signal design teams through full cycle (architecture to tape-out), plan execution across advanced CMOS nodes, manage external design contractors and IP vendors, enforce design-review discipline, design and verify high-speed circuits (SerDes, ADCs, DACs, clock distribution, laser/modulator drivers, TIAs), architect wireline SerDes and optical interconnect ICs, drive pre-silicon simulation and post-silicon bring-up
Seniority
Senior, hands-on IC design lead with team management
