Sr Staff Design Verification
Core
Design Verification Engineer for integrated digital, analog, and photonic devices using emulation and UVM techniques.
Role type
Sr Staff Design Verification Engineer
Builds
Integrated digital, analog, and photonic devices for AI data center infrastructure
Domain
Semiconductor / Photonics / AI Infrastructure
Deliverable
production ML models
Required skills
UVM, SystemVerilog, Python, Real Number Modeling (RNM), AMS verification, mixed-signal simulation, emulation, post-silicon validation, formal verification, behavioral modeling, IP integration
Preferred skills
post-silicon validation and debug, AMS verification
Technologies
Xcelium, ModelSim, Questa, VCS
Responsibilities
Define and enhance DV methodologies for integrated devices with emphasis on emulation; Create and execute test plans to ensure high-quality tapeouts; Collaborate with architects and designers to define validation flows; Create reusable and scalable test bench components; Close coverage and finish all DV signoff requirements; Work on block level and full chip design verification; Integrate analog design IPs and develop verification environments; Work with analog and digital design engineers to create behavioral models and integrate models/testcase/checkers
Seniority
Sr Staff, hands-on IC