Sr. Engineer, SoC Design Verification
Core
Pre-silicon verification of DFD logic in advanced AI SoCs, driving coverage of debug, test, and bring-up features critical to silicon success.
Role type
Senior IC SoC Design Verification Engineer
Builds
High-performance AI chiplets and SoCs
Domain
Semiconductor / AI Hardware
Deliverable
production ML models
Required skills
UVM, DFT/DFD verification, scan logic verification, on-chip trace logic verification, Siemens Tessent flows, iJTAG, verification automation, CocoTB familiarity
Preferred skills
Silicon debug/test infrastructure knowledge, cross-functional technical discussion skills
Technologies
UVM, Siemens Tessent, iJTAG, CocoTB, JTAG, scanchain
Responsibilities
Develop and own verification environments for DFD logic across AI chiplets and SoCs; Write, refine, and execute test scenarios for scan, MBIST, array dump, and clock-stop features; Analyze coverage gaps, debug failures, and collaborate closely with DFT and RTL teams; Automate flows for JTAG/scanchain testing and integrate AI productivity tools
Seniority
Senior, hands-on IC
