Tech Lead Analog Mixed-Signal IC Layout Engineer
Core
Design and verification of blocks using leading edge methodology and tools for high-performance compute and networking standards in advanced CMOS process nodes.
Role type
Tech Lead Analog Mixed-Signal IC Layout Engineer
Builds
ASICs for rack-scale AI infrastructure integrating CXL, Ethernet, NVLink, PCIe, and UALink technologies
Domain
Semiconductor / VLSI / Computer Architecture
Deliverable
production ML models
Required skills
RTL design languages (Verilog, System Verilog), UVM verification, Python/Perl scripting, C/C++, VLSI design and circuits, Computer Architecture
Preferred skills
High-speed interfaces (PCIe, DDR, HBM, Serdes), Synopsys EDA tools, Analog/Mixed-Signal Layout
Responsibilities
Design and/or verification of blocks using leading edge methodology and tools
Seniority
Senior, hands-on IC
