Teach Lead Physical Design Engineer
Core
Senior Physical Design Engineer developing high-speed transceiver IPs for next-generation AI infrastructure on advanced technology nodes.
Role type
Senior IC physical design engineer (high-speed transceivers)
Builds
High-performance transceiver IPs and chiplet-based SoC designs
Domain
Semiconductor / High-speed connectivity / AI infrastructure
Required skills
Floorplanning, placement, CTS, routing, IR drop mitigation, DRC/LVS/ANT/ERC signoff, timing closure, high-speed IP integration, Tcl/Python/Perl scripting
Preferred skills
Advanced technology node experience (3nm), hierarchical design, physical-aware synthesis, high-frequency datapath/DSP design
Technologies
ICC2, Innovus, Voltus, RedHawk, Calibre, Tcl, Python, Perl
Responsibilities
Perform block-level and top-level physical implementation including floorplanning, placement, CTS, routing, and physical verification. Collaborate with RTL and STA teams for timing, area, and power convergence. Apply advanced techniques for multiple voltage/frequency domains and hierarchical design. Conduct EM/IR analysis, congestion analysis, and clock skew optimization. Integrate IPs with attention to physical interfaces and timing alignment. Support floorplan development and chip partitioning. Perform ECO implementation and assist with tapeout signoff. Ensure clean DRC, LVS, ANT, CELL, and ERC databases. Develop automation scripts to improve physical design flows.
Seniority
Senior, hands-on IC
