Principal / Senior Principal Design Verification Engineer- CXL / PCIe / Ethernet
Core
Lead verification strategy and execution for next-generation connectivity IPs and SoCs powering AI and cloud infrastructure.
Role type
Principal / Senior Principal Design Verification Engineer
Builds
Scalable UVM/System Verilog verification environments, reusable VIPs, and verification infrastructure for CXL, PCIe, and Ethernet protocols.
Domain
Semiconductor hardware design, high-speed interconnects, AI infrastructure, data center SoCs
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
System Verilog, UVM, constrained-random verification, coverage-driven methodologies, assertions (SVA), functional coverage, protocol compliance, RTL debugging, simulation (Synopsys VCS/Cadence Xcelium/Siemens Questa), technical leadership, cross-functional collaboration, mentorship
Preferred skills
CXL protocols, PCIe layers, Ethernet MAC/PCS/PMA, coherency protocols, high-speed SerDes, DDR/LPDDR/HBM, AI accelerator connectivity, chiplet-based systems, formal verification, scripting (Python/Perl/Tcl), emulation/FPGA prototyping
Technologies
UVM, System Verilog, SVA, Synopsys VCS, Cadence Xcelium, Siemens Questa, CXL, PCIe, Ethernet, DDR, LPDDR, HBM, FPGA, Emulation
Responsibilities
Define verification strategies and methodologies for complex IPs and SoC subsystems; Architect and develop scalable verification environments; Lead technical reviews and drive coverage closure; Mentor verification engineers and establish engineering standards; Collaborate with architecture, RTL, firmware, and validation teams; Debug complex RTL, protocol, and timing issues.
Seniority
Principal / Senior Principal, hands-on IC with strategic leadership
