Senior Digital Design Engineer
Core
Design and integrate high-performance connectivity silicon (PCIe, Ethernet, SerDes) for rack-scale AI infrastructure.
Role type
Senior IC digital design engineer (connectivity silicon)
Builds
High-bandwidth connectivity chips for CPUs, GPUs, memory, storage, and networking devices
Domain
Semiconductor / AI Infrastructure / High-performance connectivity
Deliverable
production ML models | product features
Required skills
RTL design (SystemVerilog/Verilog), PCIe/Ethernet controller design, SerDes integration, timing closure, synthesis, block-level and full-chip development, Python/Perl scripting
Preferred skills
PCIe Gen 6/7 or UALink experience, advanced process nodes (16nm or smaller), PAD design, DFT, floor planning, FPGA prototyping
Technologies
SystemVerilog, Verilog, Synopsys, Cadence, Python, Perl
Responsibilities
Develop micro-architecture and implement synthesizable RTL for PCIe/Ethernet controllers and SerDes IP; Integrate controller, SerDes, and processor IP while partnering with verification and physical design teams; Drive synthesis, timing analysis, and design-quality reviews; Collaborate with firmware teams to validate hardware-software interfaces; Use scripting to automate design workflows and improve productivity.
Seniority
Senior, hands-on IC
