Digital Design Manager
Core
Lead day-to-day DFT architecture and execution for signal-conditioning products to ensure high-quality silicon for rack-scale AI infrastructure.
Role type
Senior IC DFT Manager (Signal Conditioning)
Builds
Highly testable, high-quality silicon for PCIe and Ethernet connectivity products
Domain
Semiconductor / AI Infrastructure / High-Speed Connectivity
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
DFT architecture planning, scan insertion, ATPG, compression, MBIST, LBIST, JTAG/IJTAG, SerDes physical-layer understanding, signal integrity, advanced packaging test, ATE cost analysis, yield diagnostics, cross-functional technical leadership
Preferred skills
2.5D/3D integration, silicon interposers, TSVs, hybrid bonding, micro-bumps, chiplets, KGD strategies, IEEE 1838/1149.1/1687 standards, PCIe/Ethernet/UALink validation, OSAT engagement
Technologies
Synopsys DFT Compiler, TetraMAX, DFTMAX, Siemens Tessent, ATE platforms, wafer probe
Responsibilities
Define DFT plans for high-speed PCIe and Ethernet products; Develop test-access and diagnostic strategies for die-to-die and package-level integration; Drive scan insertion, ATPG, and BIST requirements; Collaborate on yield learning and failure analysis; Mentor DFT engineers and coordinate execution across product milestones
Seniority
Senior, hands-on IC with mentorship responsibilities
