Lead DFT Engineer
Core
Architecting end-to-end Design for Test (DFT) strategies for complex SoCs to ensure manufacturability, reliability, and high test coverage for edge-to-cloud computing chips.
Role type
Lead DFT Engineer
Builds
Data center chips for edge deployment
Domain
Semiconductor design / AI hardware
Deliverable
production ML models
Required skills
DFT architecture, Hierarchical DFT, Scan compression, Boundary Scan, MBIST, In-System Test (IST), Power-on Self-Test (POST), ATPG, IJTAG, FinFET node experience, Low-power DFT
Preferred skills
Leadership in DFT, Cross-functional collaboration with Design/Physical Design/Yield teams, Post-silicon validation on ATE
Technologies
Synopsys TestMAX, Siemens/Mentor Tessent, Cadence Modus
Responsibilities
Define and implement end-to-end DFT architecture for complex SoCs; Develop strategies for In-System Test (IST) and power-on self-test (POST); Oversee scan insertion, ATPG, and Memory/Logic BIST; Collaborate with Design, Physical Design, and Yield teams; Lead the bring-up and debug phase on ATE to root-cause silicon failures.
Seniority
Lead, hands-on IC with mentorship
