Principal Design Verification Engineer- SerDes/PHY IP
Core
Architect and execute functional verification for high-speed SerDes/PHY IP (PMA, PCS, PHY-MAC) powering rack-scale AI infrastructure.
Role type
Principal Design Verification Engineer (SerDes/PHY IP)
Builds
High-speed serial connectivity blocks (UALink, UCIe, PCIe Gen 6/7, Ethernet) for AI platforms
Domain
Semiconductor IP / High-Speed Serial Connectivity / AI Infrastructure
Deliverable
production ML models
Required skills
SystemVerilog, UVM, Analog/Mixed-Signal Co-simulation, Real Number Modeling (RNM), Coverage Closure, Debugging, Testbench Architecture
Preferred skills
Python/Perl Scripting, Emulation Platform Experience, Post-Silicon Bring-up, Multi-disciplinary Leadership
Technologies
SystemVerilog, UVM, Palladium, Veloce, ZeBu, PCIe Gen 6/7, UALink, UCIe, Ethernet
Responsibilities
Architect UVM-based verification environments for SerDes/PHY IP; Develop SystemVerilog/UVM testbenches, sequences, and scoreboards; Lead coverage analysis and closure for high-speed serial links; Verify PHY behavior against industry specifications (PCIe, UALink, UCIe, Ethernet); Mentor junior DV engineers and set technical direction.
Seniority
Principal, hands-on IC with mentorship
