Lead Logic Design for UALink IP/Subsystem Engineer
Core
Lead RTL and microarchitecture development for UALink-based IP/subsystems, focusing on high-bandwidth, low-latency data movement and scalable interconnect design.
Role type
Senior IC logic design engineer (interconnect IP)
Builds
UALink IP/subsystems for rack-scale AI infrastructure
Domain
Semiconductor / High-speed interconnects / AI infrastructure
Deliverable
production ML models
Required skills
RTL design, microarchitecture, SystemVerilog, Verilog, high-speed interconnects, data movement, flow control, arbitration, buffering, CDC, lint, synthesis, timing analysis, silicon debugging, technical leadership
Preferred skills
UALink experience, PCIe, CXL, CHI, CCIX, Ethernet, AI/accelerator SoCs
Technologies
SystemVerilog, Verilog, UALink, PCIe, CXL, CHI, CCIX, Ethernet
Responsibilities
Lead UALink IP/subsystem RTL development, translate protocol requirements into microarchitecture, design high-performance control and data-path logic, optimize for performance/area/power/latency, debug functional and integration issues, review RTL and mentor engineers, support silicon debug
Seniority
Senior, hands-on IC
