Manager, Digital Design
Core
Lead front-end digital design of high-performance PCIe, CXL, UAL, and ethernet devices for rack-scale AI infrastructure.
Role type
Senior Manager, Digital Design (IC/ASIC)
Builds
Custom connectivity solutions and standards-based portfolio products for hyperscalers and ecosystem partners
Domain
Semiconductor hardware design, AI infrastructure, high-speed interconnects
Deliverable
production ML models | product features | infrastructure
Required skills
PCIe/CXL/UAL/ethernet digital design, RTL development, chip development lifecycle management, team leadership (6-8 engineers), cross-functional collaboration
Preferred skills
RTL quality methodologies, design checklists and signoff criteria, large physical floorplan design, SoC/ASIC program management
Technologies
PCIe, CXL, UAL, ethernet, RTL, synthesis, timing closure, physical design, DFT, verification
Responsibilities
Lead end-to-end chip development from requirements to tape-out; drive delivery of complex devices; partner with architecture teams to translate requirements into digital implementations; establish design standards and review gates; mentor digital design engineers; resolve design and integration issues
Seniority
Senior Manager, hands-on technical leadership
