Senior STA Engineer
Core
Own Static Timing Analysis (STA) and timing signoff for complex ASIC/SoC designs from synthesis through tape-out.
Role type
Senior IC STA Engineer (ASIC/SoC)
Builds
ASIC/SoC chips with end-to-end scale-up and scale-out connectivity
Domain
Semiconductor / VLSI / ASIC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Static Timing Analysis, timing closure, Synopsys PrimeTime, Cadence Tempus, SDC constraints, MCMM/MMMC, OCV/AOCV/POCV, clock tree analysis, Tcl scripting, ASIC/SoC design flows
Preferred skills
Python/Perl scripting, mentoring junior engineers, flow optimization
Technologies
Synopsys PrimeTime, Cadence Tempus, Tcl, Python, Perl
Responsibilities
Own STA and timing signoff activities from synthesis through physical design and tape-out; Perform MCMM/MMMC timing analysis across all functional and test modes; Analyze and debug setup, hold, recovery, removal, min/max, and clock-related violations; Develop, review, and validate SDC constraints including clocks, generated clocks, I/O delays, false paths, multicycle paths, and timing exceptions; Perform detailed clock tree and clock timing analysis including skew, latency, uncertainty, jitter, and clock reconvergence; Drive timing closure in collaboration with RTL, synthesis, physical design, and ECO teams; Analyze critical timing paths and recommend design, synthesis, placement, routing, or ECO solutions; Perform timing analysis considering OCV/AOCV/POCV, derates, SI/crosstalk, and process-voltage-temperature variations; Review timing constraints and methodology to ensure signoff-quality timing analysis; Support timing ECOs and evaluate their impact across multiple corners and modes; Develop and maintain Tcl/Python automation for STA analysis, report generation, and flow optimization; Debug complex timing issues and provide technical guidance to junior STA engineers; Participate in methodology development, flow improvements, and timing signoff reviews; Coordinate with cross-functional teams to ensure project milestones and tape-out schedules are achieved
Seniority
Senior, hands-on IC
