Advanced Package Engineer, Principal
Core
Lead R&D for advanced packaging of optical chips (NPO and CPO) for scale-up and scale-out AI infrastructure.
Role type
Principal Advanced Packaging Engineer (senior IC)
Builds
Next-generation photonics products (NPO and CPO) for AI infrastructure
Domain
Semiconductor manufacturing / Silicon Photonics / Advanced Packaging
Deliverable
production ML models | product features
Required skills
Advanced packaging processes (2.5D/3D integration, flip-chip, hybrid bonding, Cu pillar, TSV, RDL, overmold), Silicon photonics chip packaging, EIC-to-PIC integration, Packaging material selection and qualification, OSAT and tool vendor partnership, PDK development and design rule authoring, Yield analysis and reliability characterization (Cpk, SPC)
Preferred skills
CPO or NPO product development, Optical coupling and waveguide alignment, Photonics chip design, DFM and DFT for advanced packaging
Technologies
CXL, Ethernet, NVLink, PCIe, UALink, COSMOS
Responsibilities
Lead R&D for advanced packaging of optical chips; Define and optimize wafer-level, panel-level, or die-level packaging process flows; Drive EIC-to-PIC integration; Select and qualify packaging materials; Partner with OSAT and tool vendors; Characterize and improve yield and reliability; Develop and maintain packaging PDKs and design rules
Seniority
Principal, hands-on IC with technical leadership
