Product Tech Lead
Core
Architect and deliver connectivity silicon for rack-scale AI infrastructure, owning RTL design execution for complex blocks.
Role type
Senior IC digital design engineer (connectivity silicon)
Builds
Custom connectivity chips (PCIe, CXL, Ethernet, NVLink, UALink) for hyperscalers and AI clusters
Domain
Semiconductor / AI Infrastructure / High-speed interconnects
Required skills
RTL design (Verilog/SystemVerilog), synthesis flows, timing closure, CDC, low-power design, high-speed serial interfaces, SoC integration
Preferred skills
PCIe Gen5/Gen6, CXL, UALink, UCIe, Ethernet MAC/PCS, formal verification, emulation, advanced process nodes (7nm/5nm)
Technologies
Verilog, SystemVerilog, PCIe, CXL, Ethernet, NVLink, UALink, 7nm, 5nm
Responsibilities
Own RTL design from microarchitecture through synthesis sign-off; Partner with architecture to translate specs into implementation-ready microarchitecture; Collaborate with verification, DFT, and physical design teams; Mentor junior engineers and contribute to design methodology; Debug complex pre-silicon and post-silicon issues; Drive structured design decisions for tapeout schedules
Seniority
Senior, hands-on IC
