Senior Engineer CAD, Physical Verification
Core
Develop and improve physical verification tools, rule decks, and flows for CMOS designs to ensure design correctness and manufactability.
Role type
Senior IC CAD/Physical Verification Engineer
Builds
Physical verification toolchains and rule decks for HBM, DRAM, and new memory technologies
Domain
Semiconductor manufacturing / Physical Design Verification
Required skills
SVRF/TVF for Calibre, Python, Perl, Linux/Unix shell scripting, DRC/LVS methodologies, DFM, electrical reliability verification
Preferred skills
CMOS process fundamentals, antenna/ESD/latch-up checks, parasitic extraction flows, AI-assisted automation workflows
Technologies
Calibre, Linux, Python, Perl, Copilot-based assistants, agentic AI flows
Responsibilities
Develop and improve physical verification tools, rule decks, and methodologies; Debug and support in-house and commercial EDA tools; Collaborate with design, layout, and process teams to address verification challenges; Innovate verification workflows through AI-assisted automation; Evaluate emerging EDA technologies and document processes
Seniority
Senior, hands-on IC
