Verification Engineer
Core
Developing and enhancing SystemVerilog/UVM-based testbenches to verify complex design blocks (IP, Sub-system, SoC) including PCIe-based subsystems for client, server, graphics, and semi-custom interconnects.
Role type
Senior IC verification engineer (PCIe/SoC)
Builds
Production verification environments and reusable infrastructure for ASIC designs
Domain
Semiconductor / Hardware Verification
Required skills
SystemVerilog, UVM, PCIe protocol verification, testbench architecture, coverage-driven verification, mentoring
Preferred skills
ASIC verification (IP/Sub-system), PCIe Gen3/4/5, Perl/Ruby/Make scripting, RTL design, formal verification
Technologies
SystemVerilog, UVM, PCIe, Perl, Ruby, Make
Responsibilities
Develop and enhance verification testbenches, drive verification closure using coverage metrics, mentor junior engineers
Seniority
Senior, hands-on IC
