Senior Engineer IP Verification - Digital Design Verification
Core
Define verification scope and strategy for block/chip RTL verification of DRAM architectures, developing testbenches and vectors to demonstrate readiness for tapeout.
Role type
Senior IC digital design verification engineer (DRAM)
Builds
DRAM memory blocks and chips
Domain
Semiconductor / Memory / Digital Design
Required skills
RTL verification, SV-UVM, directed/constrained-random testing, functional coverage analysis, RTL debugging, Perl scripting, Python scripting, digital circuit understanding
Preferred skills
AI tool adoption for verification workflows, international collaboration
Technologies
Virtuoso, Xcellium, Simvision, Verdi/Verisium, SV, UVM
Responsibilities
Define verification scope and strategy; Develop and maintain SV-UVM testbenches; Run regressions and analyze failures; Close coverage metrics; Debug RTL/testbench issues; Partner with design engineers; Provide verification status to stakeholders
Seniority
Senior, hands-on IC
