Principal Engineer / MTS, PDE Package Design
Core
Own package architecture and execution from feasibility through tape-out, qualification, and production readiness for memory and storage solutions.
Role type
Principal Engineer / MTS, PDE Package Design
Builds
Manufacturable, reliable, and scalable silicon packages for DRAM, NAND, and NOR memory products
Domain
Semiconductor manufacturing / Memory and storage
Required skills
Package architecture, silicon-package co-design, stack-up planning, I/O and interconnect planning, substrate layout, routing, power delivery, signal return paths, design verification, manufacturability, assembly processes, substrates, materials, reliability, failure mechanisms, Cadence Allegro Package Designer / SiP Layout, design-rule and review workflows, technical leadership, mentoring, stakeholder communication, AI tool literacy
Preferred skills
None stated
Technologies
Cadence Allegro Package Designer, SiP Layout
Responsibilities
Own package architecture and execution from feasibility through tape-out, qualification, and production readiness; Serve as technical authority for complex package issues leading cross-functional reviews and risk closure; Advance design rules, methodologies, automation workflows, and technology roadmaps; Represent packaging team in Silicon–package–board co-design integrating floorplan, interface, interconnect, power, signal, thermal, and mechanical requirements
Seniority
Principal / MTS, organization-wide impact on roadmaps and standards
