Interface Design Architect, HBM - DMTS
Core
Architect and deliver high-speed memory interface blocks (HBM, DDR, LPDDR) and subsystems from definition through silicon bring-up and debug for advanced heterogeneous systems.
Role type
Senior IC Interface Design Architect (HBM/High-Speed Memory)
Builds
High-performance HBM, CPO, and chiplet-based memory subsystems for AI, ML, and HPC workloads
Domain
Semiconductor / High-Speed Memory Interfaces / Analog & Mixed-Signal Design
Required skills
HBM/DDR/LPDDR interface architecture, Analog and mixed-signal circuit design, RTL design and verification, Clocking and training/calibration, Power management and error handling, Front-end implementation and synthesis, Technical project leadership
Preferred skills
CPO system architecture, Silicon-photonics integration, UCIe and chiplet architectures, Transistor-level design and analog simulation (FastSPICE/HSPICE), 2.5D/3D packaging technologies, Signal and power integrity analysis, JEDEC/DFI standards contribution
Technologies
Verilog, SystemVerilog, FastSPICE, HSPICE, HBM, DDR, LPDDR, CPO, UCIe, 2.5D/3D packaging
Responsibilities
Define HBM PHY and controller-to-PHY requirements; Balance bandwidth, latency, power, and area trade-offs; Lead architecture of analog, mixed-signal, and digital interface functions; Partner with package and signal integrity teams; Lead root-cause analysis of pre- and post-silicon issues; Serve as technical project lead for interface programs; Research next-generation HBM and heterogeneous-integration architectures; Mentor engineers on architecture and build methods
Seniority
Senior, hands-on IC with technical leadership
