Staff Signal Integrity Engineer
Core
Staff Signal Integrity Engineer owning end-to-end SI/PI architecture, analysis, and signoff for next-generation mobile, compute, and automotive platforms.
Role type
Staff individual contributor Signal Integrity Engineer
Builds
High-performance, high-quality, low-power SoCs and connectivity platforms
Domain
Semiconductor hardware design (ASIC/SoC), high-speed digital interfaces, and system power integrity
Required skills
Signal Integrity (SI), Power Integrity (PI), high-speed interface design, transmission line theory, electromagnetic (EM) fundamentals, jitter/noise coupling analysis, cross-functional technical leadership, design convergence, standards compliance (JEDEC, PCI-SIG, MIPI, IEEE), pre-silicon modeling, silicon debugging, mentorship
Preferred skills
Packaging technologies (FCBGA, 2.5D/3D), data center and server products, patents, standards contributions, published conference work
Technologies
HFSS, ADS, Sigrity, CST, SIwave, HSPICE, VNA, TDR, real-time oscilloscopes
Responsibilities
Own end-to-end SI/PI closure from pre-silicon to production; define design targets and layout guidelines for high-speed interfaces; influence architecture decisions early in the product lifecycle; drive new IP co-design across IC/IO/PHY, package, and PCB; lead debug of eye collapse, jitter margin, crosstalk, and power noise issues; establish company-wide SI/PI methodologies and golden methods; mentor senior engineers
Seniority
Staff, hands-on individual contributor with strategic influence
