ASIC Modelling Engineer, Senior - Cork, Ireland
Core
Define, model, design, optimize, verify, validate, implement, and document IP (block/SoC) development for high performance, high quality, low power products, specifically focusing on the memory subsystem of new generation Qualcomm SoCs.
Role type
Senior ASIC Modelling Engineer
Builds
Memory infrastructure, coherency protocols, NoC interconnect fabrics, system cache, and memory controller for Qualcomm SoCs.
Domain
Semiconductor / SoC Design
Deliverable
production ML models
Required skills
C++, SystemC, Scripting languages (Python, Shell), Cache architecture, Memory controller architecture, CPU/Graphics/Multimedia architecture, On-Chip Interconnection Protocols (AXI, CHI), RTL design
Preferred skills
None explicitly stated as preferred, listed under 'We'd love to see' which are treated as required skills in the extraction above.
Technologies
C++, SystemC, Python, Shell, AXI, CHI
Responsibilities
Model the pathway to memory infrastructure including coherency protocols and NoC interconnect fabrics; Conduct exploration campaigns to identify opportunities for system cost, performance, and power improvements.
Seniority
Senior, hands-on IC
